1. Field of the Invention
The present invention relates to a storage device.
2. Description of the Related Art
At present, information devices such as a computer use a large number of storage devices to record information (data) As such storage devices, a high-density DRAM (dynamic random-access memory) which can be operated at high speed is widely used (for example, see cited non-patent reference 1).
[Cited Non-Patent Reference 1]
“VLSI MEMORY” written by Ito Kioo, published by Baifuukan Publishing Company, 1994, Nov. 5, pp. 3 to 4.
The above-mentioned storage device for recording information is requested to hold recorded information by a method as simple as possible at a low voltage.
However, since the above-mentioned DRAM is a volatile memory having an extremely short information holding time and in which recorded information is lost once it is de-energized, it should be refreshed very frequently (that is, an operation for rewriting written information after the written information has been read out and again amplified). Therefore, its circuit design becomes complex and its power consumption increases unavoidably.
For this reason, a storage device of which power consumption can be reduced and which has characteristics that can replace the DRAM, for example, has been requested so far.
Since the above-mentioned DRAM is complex in manufacturing process as compared with an ordinary logic circuit LSI (large-scale-integration) and a signal processing LSI which are suitable for use with consumer electronic devices, a problem arises, in which a storage device will become costly inevitably.
As a storage device which has a possibility to realize the above-mentioned requirements, there is known a storage device having an arrangement shown in FIG. 1, for example.
FIG. 1 of the accompanying drawings is a schematic cross-sectional view showing a fundamental arrangement of a storage device, in particular, its memory element in an enlarged-scale.
As shown in FIG. 1, a memory element 20 has an arrangement in which an interelectrode material 23 is sandwiched between two electrodes (first and second electrodes 21 and 22 in the case of FIG. 1).
The storage device including the memory element 20 having such arrangement uses an ionic conductor as the interelectrode 23, for example, and further any one of the two electrodes 21, 22 (for example, the first electrode 21) contains a metal which is diffused into the ionic conductor as ions. Thus, when a voltage is applied to the two electrodes 21, 22 of the memory element 20, electric charges are supplied to the interelectrode material 23 and the metal which was contained in the first electrode 21 is diffused into the interelectrode material 23 composed of the ionic conductor as ions, whereby electric characteristics such as a resistance or a capacitance in the ionic conductor are changed to record information on the memory element 20.
Next, the manner in which such storage device is operated to record (write and erase) information in actual practice will be described more specifically.
A recording operation to change the resistance of the memory element 20 from a high level to a low level will hereinafter be defined as “writing” of information, and a recording operation to change the resistance of the memory element 20 from a low level to a high level will hereinafter be referred to as “erasing” of information.
When the storage device writes information on the memory element 20, for example, a write voltage (positive voltage) is applied to the first electrode 21 through an interconnection (not shown) connected to the first electrode 21, for example, whereby the metal contained in the first electrode 21, for example, is ionized, diffused into the ionic conductor, bonded to electrodes and thereby deposited. As a result, the resistance of the ionic conductor goes to a low level and the resistance of the memory element 20 also goes to a low level, thereby making it possible to write information in the memory element 20.
When information is erased from the memory element 20, for example, an erase voltage (negative voltage) with polarity opposite to that of the write voltage is applied to the second electrode 22 through an interconnection (not shown) connected to the second electrode 22, for example. In consequence, the metal that has been deposited in the ionic conductor is ionized again and returned to the first electrode 21, whereby the resistance of the ionic conductor goes back to the original high level and the resistance of the memory element 20 goes to a high level, thereby making it possible to erase information from the memory element 20.
FIGS. 2A, 2B and FIGS. 3A, 3B show a series of recording operations corresponding to a series of recording operations executed by the above-mentioned storage device (for example, DRAM).
FIGS. 2A, 3A show the recording operations of the DRAM, and FIGS. 3A, 3B show the recording operations of the storage device that includes the memory element 20 shown in FIG. 1.
FIGS. 2A, 2B show the manner in which information is read out from the memory element 20 after different information has been recorded repeatedly on the memory element 20, i.e. three times. FIGS. 3A, 3B show the manner in which different information are recorded on the memory element 20 and information is read out from the memory element 20 after the same information has been recorded on the memory element 20 a plurality of times, for example, five times successively.
As is clear from FIGS. 2A, 2B and FIGS. 3A, 3B, the information writing operation at the storage device including the above-mentioned memory element 20 shown in FIG. 1 (recording operation for changing the resistance value from a high level to a low level) corresponds to writing of information “1” in the case of the DRAM and information erasing operation (recording operation for changing the resistance value from a low level to a high level) corresponds to writing of information “0” in the case of the DRAM.
In the storage device including the memory element 20 shown in FIG. 1, when information is read out from the memory element 20 after information has been written in and erased from the memory element 20 alternately and successively as shown in FIG. 2B, there arises no problem. However, when information is erased from and then read out from the memory element 20 after information has been written in the memory element 20 a plurality of times as shown in FIG. 2B, the following problem arises.
Specifically, as shown in FIG. 4, when information is repeatedly and successively written in the memory element 20, the resistance value of the memory element 20 further drops to become lower than a resistance value that has been intended to realize in the state in which information “1” should be held as the number of writing increases.
When the resistance value of the memory element 20 drops as described above, it becomes necessary to apply a large voltage to the memory element 20 to erase information from the memory element 20 next.
The memory element 20 for use with the data rewritable storage device such as the DRAM is requested to carry out recording operation in this way when information “0” and information “1” are repeatedly written in any order without limit (that is, the storage device is requested to record and read information without any limit).
This operation is such that information “0” is written on the memory element 20 after information “1” has been recorded on the memory element 20 repeatedly and continuously as shown in FIG. 3A.
Accordingly, when the storage device including the memory element 20 shown in FIG. 1 realizes a storage device which can replace the DRAM, for example, in actual practice, it becomes necessary to set a voltage applied to the memory element 20, required to erase information, to a large value on the assumption that information will be erased from the memory element 20 after information has been written repeatedly (see FIG. 3B).
However, in such case, it takes a lot of time to erase recorded information from the memory element 20, for example, and operation speed of the memory element 20 itself decreases unavoidably. In particular, when information is written in the memory element 20 after recorded information has been erased from the memory element 20 repeatedly and continuously in the manner opposite to the case assumed in FIG. 3B, the operation speed of the memory element 20 itself decreases considerably.
Having described so far the case in which the resistance value of the memory element 20 is further changed as the number of writing increases when information was written in the memory element 0 having the arrangement shown in FIG. 1 (see FIGS. 2A, 2B), it may be considered that, depending upon an arrangement of a memory element, when information is written in such memory element repeatedly and continuously, a threshold voltage of the memory element, for example, will change as the number of writing increases.
In such case, as mentioned before, it takes plenty of time to erase recorded information from the memory element, and hence operation speed of the memory element itself decreases unavoidably.